--test rundy 32
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity test_r32 is
    Port ( din : in  STD_LOGIC_VECTOR (7 downto 0);
		dout : out  STD_LOGIC_VECTOR (7 downto 0));
end test_r32;


architecture Behavioral of test_r32 is

component runda32 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		rdk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda32;

component invrunda32 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		rdk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda32;

signal rdin, rir, iro : STD_LOGIC_VECTOR (127 downto 0);
begin
rdin(7 downto 0) <=  din(7 downto 0);
rdin(127 downto 8) <= X"AFB3299C0A397BADD4A3C736294B45";

r: runda32 port map (rdin, X"FF99123867BC23AD435CA23F456B5678", X"FF99123867BC23AD435CA23F456B5678", rir);
ir: invrunda32 port map (rir, X"FF99123867BC23AD435CA23F456B5678", X"FF99123867BC23AD435CA23F456B5678", iro);

dout(7 downto 0)<=iro(7 downto 0);
end Behavioral;
